Physical Design & Verification - Batch 2
About The Course
This course provides a thorough examination of the physical design and implementation phases of ASIC development. Students will learn the intricacies of translating logical design into physical layouts, covering key aspects such as floorplanning, placement, routing and signing off with industry standard Tools. This course also includes practical techniques for optimizing power. Performance and area (PPA). Ensuring that designs meet stringent requirements before fabrication.
What Will You Learn?
You will master the fundamentals of circuit theory, network analysis, and devices, alongside advanced topics like logic synthesis, timing analysis, and physical design flow. The course will equip you with skills in static timing analysis, design for testability, and post-layout simulation, and you'll learn to use industry-standard tools for synthesis, optimization, and power analysis. By the end, you'll be proficient in setting up and analyzing design constraints, performing logic equivalency checks, and executing a complete physical design flow.
Training Outcomes
Upon completing the training, participants will:
Agenda
- Introduction To Logic Synthesis
- Mapping To Target Technology
- Synthesis Constraints
- Synthesis Under PVT constraints
- Introduction To Synthesis Reports
- Introduction to Physical Synthesis
- Synthesis Optimization Techniques
- Logic Equivalency Check
- Introduction to Physical Design
- PD flow stages & Data preparation
- Multi Mode Multi Corner Analysis
- Floorplan
- Power Plan
- Placement
- Clock Tree Synthesis
- Routing, Physical Verification
- Signal Integrity
- Parasitic Extraction and Power Analysis
- Introduction To Static Timing Analysis
- Technology LEF Description
- Understanding Timing Arcs
- Post layout Static Timing Analysis
- Back annotation
- Sign-off checks and GDS-II Generation
Session Details
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Who can Benefit
