Agenda :

• Design Verilog HDL of 4-bit binary counter
• Test bench creation & simulation
• Perform synthesis & report readings
• Focus on constraints to obtain optimum gate level netlist
• Perform Physical design flow & Physical verification (DRC/LVS)
• Final GDSII file generation

Tools used :

Cadence Incisive/Xcelium
Cadence Genus
Cadence Innovus
Cadence PVS

Agenda :

• Introduction to Custom IC Design Flow
• MOSFET Characteristics
• Voltage Transfer Characteristics of CMOS Inverter
• Schematic capture using the Virtuoso schematic editor
• Creating layouts using the Virtuoso layout editor
• Physical verification & parasitic extraction using assura/pvs
• Post layout simulation (back annotation)
• GDSII generation (Tape out)

Tools used :

Virtuoso Schematic Editor
Spectre Simulator
Virtuoso Layout Editor
Assura/PVS

Agenda :

• Design a Verilog HDL of Arithmetic & Logic Unit
• Test bench creation & Simulation
• Perform synthesis & report readings
• Focus on constraints to obtain optimum gate level netlist
• Perform Physical design flow & Physical verification (DRC/LVS)
• Final GDSII file generation

Tools used :

Cadence Incisive/Xcelium
Cadence Genus
Cadence Innovus
Cadence PVS

Agenda :

• NMOS Transistor as an Amplifier
• Design of Single Stage Common Source Amplifier with PMOS Current Mirror
• Schematic capture using Virtuoso schematic editor
• Transient, DC & AC analysis of the design using spectre simulator
• Creating layouts using the Virtuoso layout editor
• Physical verification & parasitic extraction using Assura/pvs
• Post layout simulation (back annotation)

Tools used :

Virtuoso Schematic Editor
Spectre Simulator
Virtuoso Layout Editor
Assura/PVS

Agenda :

• Design a Verilog HDL of UART
• Test bench creation & Simulation
• Perform Synthesis & report readings
• Focus on constraints to obtain optimum gate level netlist
• Perform Physical Design flow & Physical Verification (DRC/LVS)
• Final GDSII file generation

Tools used :

Cadence Incisive/Xcelium
Cadence Genus
Cadence Innovus
Cadence PVS

Agenda :

• Design of Two Input CMOS NAND Gate
• Schematic capture using Virtuoso schematic editor
• Transient DC & AC analysis of the design using Spectre simulator.
• Creating Layout using virtuoso layout editor.
• Physical verification & parasitic extraction using Assura/pvs.
• Post layout simulation (back annotation).

Tools used :

Virtuoso Schematic Editor
Spectre Simulator
Virtuoso Layout Editor

Agenda :

• Design of single-bit Full Adder
• Schematic capture using the Virtuoso schematic editor
• Transient DC & AC analysis of the design using Spectre simulator.
• Creating Layout using virtuoso layout editor.
• Physical verification & parasitic extraction using Assura/pvs.
• Post layout simulation (back annotation).
• Design a Verilog HDL of Full Adder
• Test bench creation & simulation
• Perform synthesis & report readings
• Focus on constraints to obtain optimum gate level netlist
• Perform Physical design flow & Physical verification (DRC/LVS)
• Final GDSII file generation

Tools used :

Virtuoso Schematic Editor
Spectre Simulator
Virtuoso Layout Editor
NcSim/Xcelium
Genus
Innovus
PVS

Agenda :

• Design of Differential Amplifier
• Schematic capture using the Virtuoso schematic editor
• Transient AC analysis of the design using spectre simulator
• Creating layouts using the Virtuoso layout editor
• Physical verification & parasitic extraction using assura/pvs
• Post layout simulation (back annotation)

Tools used :

Virtuoso Schematic Editor
Spectre Simulator
Virtuoso Layout Editor

Agenda :

• Design a Verilog HDL of Sequence Detector
• Test bench creation & Simulation
• Perform Synthesis & report readings
• Focus on constraints to obtain optimum gate level netlist
• Perform Physical Design flow & Physical Verification (DRC/LVS)
• Final GDSII file generation

Tools used :

Cadence Incisive/Xcelium
Cadence Genus
Cadence Innovus
Cadence PVS

Agenda :

• Design a Verilog HDL code for 4-Bit Booth Multiplier
• Test bench creation & Simulation
• Perform Synthesis & report readings
• Focus on constraints to obtain optimum gate level netlist
• Perform Physical Design flow & Physical Verification (DRC/LVS)
• Final GDSII file generation

Tools used :

Cadence Incisive/Xcelium
Cadence Genus
Cadence Innovus
Cadence PVS

Agenda :

• Schematic Capture & Simulation using Virtuoso Schematic Editor
• Creating Layout using Virtuoso Layout Editor
• Physical Verification & Parasitic Extraction
• Post layout Simulation
• GDSII generation

Tools used :

Virtuoso Schematic Editor
Spectre Simulator
Virtuoso Layout Editor

Agenda :

• Design a Verilog HDL code for Traffic Light Controller
• Test bench creation & Simulation
• Perform Synthesis & report readings
• Focus on constraints to obtain optimum gate level netlist
• Perform Physical Design flow & Physical Verification (DRC/LVS)
• Perform Post Layout Simulation
• Final GDSII file generation

Cadence Tools used :

Incisive/Xcelium
Genus
Conformal
Modus
Innovus
PVS

Agenda :

• Schematic Capture & Simulation using Virtuoso Schematic Editor
• Creating Layout using Virtuoso Layout Editor
• Physical Verification & Parasitic Extraction
• Post layout Simulation
• GDSII generation

Cadence Tools used :

Virtuoso Schematic Editor
Spectre Simulator
Virtuoso Layout Editor
Assura/PVS

Agenda :

• Design a Verilog HDL code for 4-Bit Divider
• Test bench creation & Simulation
• Perform Synthesis & report readings
• Focus on constraints to obtain optimum gate level netlist
• Perform Physical Design flow & Physical Verification (DRC/LVS)
• Final GDSII file generation

Cadence Tools used :

Incisive/Xcelium
Genus
Conformal
Modus
Innovus
PVS

Agenda :

• Schematic Capture & Simulation using Virtuoso Schematic Editor
• Creating Layout using Virtuoso Layout Editor
• Physical Verification & Parasitic Extraction
• Post layout Simulation
• GDSII generation

Cadence Tools used :

Virtuoso Schematic Editor
Spectre Simulator
Virtuoso Layout Editor
Assura/PVS

Agenda :

• Design a Verilog HDL code for 32-bit pipelined multiplier
• Test bench creation & Simulation
• Perform Synthesis & report readings
• Focus on constraints to obtain optimum gate level netlist
• Perform Physical Design flow & Physical Verification (DRC/LVS)
• Final GDSII file generation

Cadence Tools used :

Incisive/Xcelium
Genus
Conformal
Modus
Innovus
PVS

Credits / Reference : Washington State University, USA. EE 434: ASIC & Digital Systems

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Schematic Capture & Simulation using Virtuoso Schematic Editor
• Delay Estimation using calculator
• Creating Layout using Virtuoso Layout Editor
• Physical Verification & Parasitic Extraction
• Post layout Simulation

Cadence Tools used :

Virtuoso Schematic Editor
Spectre Simulator
Virtuoso Layout Editor
Assura/PVS

Credits / Reference : Washington State University, USA. EE 434: ASIC & Digital Systems & Biju Patnaik University of Technology, Rourkela, Odisha. REC6C203, 2019-2020

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Design a Verilog HDL code for Vending Machine
• Test bench creation & Simulation
• Perform Synthesis & PPA reports analysis
• Focus on constraints to obtain optimum gate level netlist
• Perform Physical Design & Physical Verification (DRC/LVS)
• Timing & Power Analysis
• Post-layout simulation
• Final GDSII file generation

Cadence Tools used :

Cadence Xcelium
Genus
Conformal LEC
Innovus
Tempus
Voltus & PVS

Credits / Reference : All Rights & Credits to NIT Trichy, University of Washington & Farmingdale-state-college.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Design of Differential Amplifier
• Schematic capture using virtuoso schematic editor
• Transient ac analysis of the design using spectre simulator
• Creating layout using virtuoso layout editor
• Physical verification & parasitic extraction using assura/pvs
• Post layout simulation (back annotation)

Cadence Tools used :

Virtuoso Schematic Editor
Spectre Simulator
Virtuoso Layout Editor

Credits / Reference : All Rights & Credits to Anna university & VTU.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Design a Verilog HDL code for Booth Multiplier
• Test bench creation & Simulation
• Perform Synthesis & PPA reports analysis
• Focus on constraints to obtain optimum gate level netlist
• Perform Physical Design & Physical Verification (DRC/LVS)
• Timing & Power Analysis
• Post-layout simulation
• Final GDSII file generation

Cadence Tools used :

Cadence Xcelium
Genus, IMC, Modus DFT
Conformal LEC
Innovus, Tempus
Voltus & PVS

Credits / Reference : All Rights & Credits to PES Univeristy, NIT Trichy & IIT Kharagpur.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Discussion on available opamp design
• Schematic capture of 4-bit R2R DAC using virtuoso schematic editor
• Transient ac analysis of the design using spectre simulator
• Creating layout using virtuoso layout editor
• Physical verification & parasitic extraction using assura/pvs
• Post layout simulation (back annotation)

Cadence Tools used :

Virtuoso Schematic Editor
Spectre Simulator
Virtuoso Layout Editor

Credits / Reference : All Rights & Credits to Aligarh Muslim University, VTU (15 scheme).

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Schematic Capture & Simulation using Virtuoso Schematic Editor
• DC, AC & Transient analysis
• Creating Layout using Virtuoso Layout Editor
• Physical Verification & Parasitic Extraction
• Post layout Simulation

Cadence Tools used :

Virtuoso Schematic Editor
Spectre Simulator
Virtuoso Layout Editor
Quantus & Assura/PVS

Credits / Reference : All Rights & Credits to Anna University, Tamil Nadu.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Design a Verilog HDL code for 8-bit magnitude comparator
• Test-bench creation & Simulation
• Code Coverage Analysis
• Perform Synthesis & PPA reports analysis
• DFT insertion
• Focus on constraints to obtain optimum gate level netlist
• Logic Equivalence check
• Perform Physical Design & Verification(DRC/LVS)
• Timing & Power Analysis
• Post-layout simulation & Final GDSII file generation

Cadence Tools used :

Cadence Xcelium
Genus, IMC, Modus DFT
Conformal LEC, Tempus
Voltus, Quantus & PVS

Credits / Reference : All Rights & Credits belong to @ CoE Pune, University of Calcutta & Sri Venkateshwara University-UP.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Discussion on available SRAM Cells
• Schematic capture of 6T - SRAM Cell using virtuoso schematic editor
• Transient analysis of the design using spectre simulator
• Creating layout using virtuoso layout editor
• Physical verification & parasitic extraction using Assura/PVS
• Post layout simulation (back annotation)

Cadence Tools used :

Virtuoso Schematic Editor
Spectre Simulator
Virtuoso Layout Editor
Voltus, Quantus & PVS

Credits / Reference : All Rights & Credits belong to VTU (2021 scheme).

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Design a Verilog HDL code for Elevator Controller
• Test-bench creation & Simulation
• Code Coverage Analysis
• Perform Synthesis & PPA reports analysis
• DFT insertion
• Focus on constraints to obtain optimum gate level netlist
• Logic Equivalence check
• Perform Physical Design & Verification(DRC/LVS)
• Timing & Power Analysis
• Post-layout simulation
• Final GDSII file generation

Cadence Tools used :

Cadence Xcelium
Genus, IMC
Modus DFT, Conformal LEC
Innovus, Tempus
Voltus, Quantus & PVS

Credits / Reference : All Rights & Credits belong to Sri Venkateshwara University-UP, J.C.Bose University of Science & Technology-Faridabad & Jawaharlal Nehru Technological University-Hyderabad.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Discussion on available D-flip flop
• Schematic capture of D-flip flop using virtuoso schematic editor
• Transient analysis of the design using spectre simulator
• Creating layout using virtuoso layout editor
• Physical verification & parasitic extraction using Assura/PVS
• Post layout simulation (back annotation)

Cadence Tools used :

Virtuoso Schematic Editor
Spectre Simulator
Virtuoso Layout Editor

Credits / Reference : All Rights & Credits belong to IIT(ISM) Dhanbad, VTU & Anna University.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• MIPS Instruction set and Algorithm
• Architectural Exploration
• Design Verilog HDL code for MIPS
• Test bench creation and Functional Simulation
• Formal Verification (Coverage Analysis)
• Perform Synthesis and PPA reports analysis
• Focus on constraints to obtain optimum gate level netlist
• Pre and Post-Synthesis Logic Equivalence Check
• synthesis with DFT

Cadence Tools used :

Cadence Incisive/ Xcelium
IMC, Genus
Modus
Conformal LEC

Credits / Reference : All Rights & Credits belong to Centurion University, University of South Florida, Osmania University, etc.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Data Preparation for Physical Design
• Floor and Power Planning
• Placement, CTS, and Routing (APR)
• Timing and Power Analysis
• Post-layout simulation and Logic Equivalence Check
• Physical Verification, DFM and Sign-off
• Final GDSII file generation

Cadence Tools used :

Cadence Innovus
Tempus, Voltus
Quantus, PVS, Xcelium
Conformal LEC & Virtuoso

Credits / Reference : All Rights & Credits belong to CoE Pune, JNTU Anantapur, University of Utah, California State University.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Sample and Hold circuit
• Opamp as Comparator
• Importing verilog code blocks into virtuoso
• R2R DAC schematic

Cadence Tools used :

Schematic capture - virtuoso schematic editor
Simulator - Spectre AMS.

Credits / Reference : All Rights & Credits belong to Anna University.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Design Analysis and Verification Plan
• Write RTL code (Verilog) for MAC Unit
• Test bench creation for Functional Simulation
• Formal Verification (Coverage Analysis)
• Design Synthesis and PPA reports analysis
• Focus on SDC constraints to obtain optimum gate-level netlist
• Design for Testability (DFT)
• Pre and Post-Synthesis Logic Equivalence Check (LEC)

Cadence Tools used :

Cadence Xcelium, IMC
RTL Joules
Genus, DFT
Conformal LEC

Credits / Reference : All Rights & Credits belong to NIT Trichy, Centurion University, Punjab Technical University, National Cheng Kung University.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• MAC Unit data preparation for Physical Design
• Floor and Power Planning
• Placement, CTS, & Routing
• Timing and Power Analysis
• Post-layout simulation and Logic Equivalence Check
• Physical Verification, DFM and Sign-off
• Final GDSII file generation

Cadence Tools used :

Cadence Innovus
Quantus, Tempus
Voltus, PVS, Xcelium
Conformal LEC and Virtuoso

Credits / Reference : All Rights & Credits belong to NIT Trichy, Centurion University, Punjab Technical University, National Cheng Kung University.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Design of two input CMOS NOR gate
• Schematic capture using virtuoso schematic editor
• Transient, dc and ac analysis of the design using spectre simulator
• creating layout using virtuoso layout editor
• physical verification and parasitic extraction using assura/pvs
• post layout simulation (back annotation)

Cadence Tools used :

Virtuoso Schematic Editor
Spectre Simulator
Virtuoso Layout Editor

Credits / Reference : All Rights & Credits belong to JNTU, Hyderabad.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Design Analysis and Verification Plan
• Write RTL code (Verilog) for PWM Generator
• Test bench creation for Functional Simulation
• Formal Verification (Coverage Analysis)
• Design Synthesis and PPA reports analysis
• Focus on SDC constraints to obtain optimum gate-level netlist
• Design for Testability (DFT)
• Pre and Post-Synthesis Logic Equivalence Check (LEC)

Cadence Tools used :

Cadence Xcelium, IMC
RTL Joules, Genus
Modus, Conformal LEC

Credits / Reference : All Rights & Credits belong to IIT Bombay, NIT Trichy.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Introduction to ASIC Physical Design, Verification and Sign-off
• PWM Generator Design Analysis and IO Planning
• Data Preparation for Physical Design
• Floor and Power Planning
• Placement, CTS, and Routing (APR)
• Timing and Power Analysis
• Post-layout simulation and Logic Equivalence Check
• Physical Verification, DFM and Sign-off
• Final GDSII file generation

Cadence Tools used :

Cadence Innovus, Tempus
Voltus, Quantus
PVS, Xcelium
Conformal LEC & Virtuoso

Credits / Reference : All Rights & Credits belong to IIT Bombay, NIT Trichy.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Introduction and Schematic Architectures of Full adder
• Schematic Capture and Simulation using Virtuoso Schematic Editor
• Delay Estimation using calculator
• Creating Layout Using Virtuoso Layout Editor
• Physical Verification & Parasitic Extraction
• Post layout Simulation

Cadence Tools used :

Simulator - Spectre
Virtuoso Layout Editor
Schematic capture
Virtuoso Schematic Editor

Credits / Reference : All Rights & Credits belong to IIT Bombay, NIT Trichy.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Design Analysis and Verification Plan
• Write RTL code (Verilog) for Serial Peripheral Interface
• Test bench creation for Functional Simulation
• Formal Verification (Coverage Analysis)
• Design Synthesis and PPA reports analysis
• Focus on SDC constraints to obtain optimum gate-level netlist
• Design for Testability (DFT)
• Pre and Post-Synthesis Logic Equivalence Check (LEC)

Cadence Tools used :

Simulator - Spectre
Virtuoso Layout Editor
Schematic capture
Virtuoso Schematic Editor

Credits / Reference : All Rights & Credits belong to IIT Bombay, NIT Trichy.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Introduction to ASIC Physical Design, Verification and Sign-off
• SPI Netlist Analysis and IO Planning
• Data Preparation for Physical Design
• Floor and Power Planning
• Placement, CTS, and Routing (APR)
• Timing and Power Analysis
• Post-layout simulation and Logic Equivalence Check
• Physical Verification, DFM and Sign-off
• Final GDSII file generation

Cadence Tools used :

Cadence Innovus, Tempus
Voltus, Quantus
PVS, Xcelium
Conformal LEC, Virtuoso

Credits / Reference : All Rights & Credits belong to Centurion University, University of South Florida, Osmania University.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Design Analysis and Verification Plan
• Write RTL code (Verilog) for Mod-10 counter
• Test bench creation for Functional Simulation
• Formal Verification (Coverage Analysis)
• Verification of RTL using Jasper Gold
• Design Synthesis and PPA reports analysis
• Focus on SDC constraints to obtain optimum gate-level netlist
• Design for Testability (DFT)
• Pre and Post-Synthesis Logic Equivalence Check (LEC)

Cadence Tools used :

Cadence Incisive/ Xcelium
Jasper Gold, Genus
IMC, Modus
Conformal LEC

Credits / Reference : All Rights & Credits belong to NIT Tiruchirappalli, NIT Silchar, NIT Patna, etc.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Introduction to ASIC Physical Design, Verification and Sign-off
• Mod-N(Mod-10) Counter Analysis and IO Planning
• Mod-N(Mod-10) Counter data preparation for Physical Design
• Floor and Power Planning,
• Placement, CTS, & Routing
• Timing and Power Analysis
• Post-layout simulation and Logic Equivalence Check
• Physical Verification, DFM and Sign-off
• Final GDSII file generation

Cadence Tools used :

Innovus, Quantus
Tempus, Voltus
PVS, Xcelium
Conformal LEC and Virtuoso

Credits / Reference : All Rights & Credits belong to NIT Tiruchirappalli, NIT Silchar, NIT Patna, etc.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Design Analysis and Verification Plan
• Write RTL code (Verilog) for FIFO
• Testbench creation for Functional Simulation
• Coverage Analysis of Testbench
• Formal Verification of RTL using Jasper Gold
• Design Synthesis and PPA reports analysis
• Focus on SDC constraints to obtain optimum gate-level netlist
• Design for Testability (DFT)
• Pre and Post-Synthesis Logic Equivalence Check (LEC)

Cadence Tools used :

Cadence Incisive/ Xcelium
Jasper Gold, Genus
IMC, Modus
Conformal LEC

Credits / Reference : All Rights & Credits belong to NIT Tiruchirappalli, NIT Silchar, NIT Patna, etc.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Introduction to ASIC Physical Design, Verification and Sign-off
• Recap of FIFO Front-end design and Report analysis
• FIFO Netlist data preparation for Physical Design
• Sanity Checks
• Floor and Power Planning,
• Placement, CTS, & Routing
• Timing and Power Analysis
• Post-layout simulation and Logic Equivalence Check
• Physical Verification, DFM and Sign-off
• Final GDSII file generation

Cadence Tools used :

Innovus, Quantus
Tempus
Voltus, PVS, Conformal LEC
Xcelium

Credits / Reference : All Rights & Credits belong to NIT Tiruchirappalli, NIT Silchar, NIT Patna, etc.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Design Analysis and Verification Plan
• Write RTL code (Verilog) for I2C
• Testbench creation for Functional Simulation
• Coverage Analysis of Testbench
• Formal Verification of RTL using Jasper Gold
• Design Synthesis and PPA reports analysis
• Focus on SDC constraints to obtain optimum gate-level netlist
• Design for Testability (DFT)
• Pre and Post-Synthesis Logic Equivalence Check (LEC)

Cadence Tools used :

Cadence Incisive/ Xcelium
IMC
Jasper Gold, Genus
Modus, Conformal LEC

Credits / Reference : All Rights & Credits belong to Centurion University Odisha, Southern Illinois University Edwardsville, etc.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Introduction to ASIC Physical Design, Verification and Sign-off
• Recap of I2C Front-end design and Report analysis
• I2C Netlist data preparation for Physical Design
• Sanity Checks
• Floor and Power Planning
• Placement, CTS, & Routing
• Timing and Power Analysis
• Post-layout simulation and Logic Equivalence Check
• Physical Verification, DFM and Sign-off
• Final GDSII file generation

Cadence Tools used :

Innovus, Quantus
Tempus, Voltus
PVS, Conformal LEC
and Xcelium

Credits / Reference : All Rights & Credits for the lab experiment belong to Centurion University Odisha, Southern Illinois University Edwardsville, etc.
"© Abhiyantha - Training Arm of Entuple Technologies Pvt. Ltd. All rights reserved. This course and its materials are protected by copyright law. Unauthorized reproduction or distribution is prohibited."

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Design Analysis and Verification Plan
• Write RTL code (Verilog) for shift and add multiplier
• Testbench creation for Functional Simulation
• Coverage Analysis of Testbench
• Formal Verification of RTL using Jasper Gold
• Design Synthesis and PPA reports analysis
• Focus on SDC constraints to obtain optimum gate-level netlist
• Design for Testability (DFT)
• Pre and Post-Synthesis Logic Equivalence Check (LEC)

Cadence Tools used :

Cadence Incisive/ Xcelium,
IMC, Jasper Gold
Genus, Modus
Conformal LEC

Credits / Reference : All Rights & Credits belong to VTU.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Design data preparation for Physical Design
• Floor and Power Planning
• Placement, CTS, & Routing
• Timing and Power Analysis
• Post-layout simulation
• Physical Verification and Sign-off
• Final GDSII file generation

Cadence Tools used :

Cadence Innovus,
Tempus
Voltus
PVS, Xcelium

Credits / Reference : All rights & credits for the lab experiment belong to VTU.
"© Abhiyantha - Training Arm of Entuple Technologies Pvt. Ltd. All rights reserved. This course and its materials are protected by copyright law. Unauthorized reproduction or distribution is prohibited."

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Introduction to Digital Circuit Design in VLSI
• Digital Circuit Implementation Topologies
• Overview of CMOS Logic Design
• Implementing Complex Boolean Expressions using CMOS
• Advantages and Disadvantages of CMOS Logic
• Schematic Capture – Designing the Boolean Expression in Cadence Virtuoso
• Simulation Setup – Configuring simulation parameters in ADE L
• Transient & DC Analysis – Evaluating circuit behavior and performance
• Propagation Delay Calculation – Setting up and analyzing timing parameters
• Q&A Session

Cadence Tools used :

Virtuoso Schematic Editor
TADE L (Analog Design Environment L)
Spectre Simulator

Credits / Reference : All rights & credits for the lab experiment belong to VTU 2022 Scheme.
This course and its materials are protected by copyright law. Unauthorized reproduction or distribution is prohibited.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Preview of Session-1
• Introduction to Euler's Path
• Stick diagram
• Layout Capture – Designing the Boolean Expression in Cadence Virtuoso
• Physical Verification –Setup and analysis of DRC and LVS using Assura
• Post Layout simulation – Evaluating circuit behavior and performance
• Propagation Delay Calculation – Setting up and analyzing timing parameters
• Q&A Session

Cadence Tools used :

Virtuoso Layout Editor
ADE L (Analog Design Environment L)
Spectre Simulator
Assura

Credits / Reference : All rights & credits for the lab experiment belong to VTU 2022 Scheme.
This course and its materials are protected by copyright law. Unauthorized reproduction or distribution is prohibited.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Brief overview of digital design flow in Cadence
• Importance of decoder circuits in digital systems
• Gate-level implementation overview
• Writing and applying SDC constraints for Pure combinational circuits
• Writing synthesizable Verilog code for 2-to-4 decoder
• Simulation using Xcelium/Incisive
• Running synthesis
• Viewing synthesis reports (area, timing, etc.)
• Implementation in Innovus
• Q&A

Cadence Tools used :

Xcelium/incisive
IMC, Genus
Innovus

Credits / Reference : All rights & credits for the lab experiment belong to VTU 2022 Scheme.
This course and its materials are protected by copyright law. Unauthorized reproduction or distribution is prohibited.

Note : Experiments are being made available for educational & informational purposes only.

Click here to Buy Recorded Session

Agenda :

• Design Analysis and Verification Plan
• Write RTL code (Verilog) for Serial Peripheral Interface
• Test bench creation for Functional Simulation
• Formal Verification (Coverage Analysis)
• Design Synthesis and PPA reports analysis
• Focus on SDC constraints to obtain optimum gate-level netlist
• Design for Testability (DFT)
• Pre and Post-Synthesis Logic Equivalence Check (LEC)

Cadence Tools used :

Simulator - Spectre
Virtuoso Layout Editor
Schematic capture
Virtuoso Schematic Editor

Credits / Reference : All Rights & Credits belong to IIT Bombay, NIT Trichy, This course and its materials are protected by copyright law. Unauthorized reproduction or distribution is prohibited.

Note : Experiments are being made available for educational & informational purposes only.

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Agenda :

• Introduction to ASIC Physical Design, Verification and Sign-off
• SPI Netlist Analysis and IO Planning
• Data Preparation for Physical Design
• Floor and Power Planning
• Placement, CTS, and Routing (APR)
• Timing and Power Analysis
• Post-layout simulation and Logic Equivalence Check
• Physical Verification, DFM and Sign-off
• Final GDSII file generation

Cadence Tools used :

Cadence Innovus, Tempus
Voltus, Quantus
PVS, Xcelium
Conformal LEC, Virtuoso

Credits / Reference : All Rights & Credits belong to Centurion University, University of South Florida, Osmania University, This course and its materials are protected by copyright law. Unauthorized reproduction or distribution is prohibited.

Note : Experiments are being made available for educational & informational purposes only.

Register Now for Free